It is essential to prepare a test circuit for the circuit demanded by the customer (hereinafter referred to as a customer circuit) when designing LSIs or the like. Conventionally, the design is carried out according to a procedure in which the test circuit or the like is embedded into the customer circuit and then placement and routing is performed. The procedure to be performed by a circuit design device that performs the design as described above will be shown in FIG. 6. Referring to FIG. 6, an internal test circuit generation processing unit 102 in the circuit design device inputs customer circuit design data 101, embeds the test circuit inside the customer circuit, and generates data including data on internal test circuit 103. A placement and routing processing unit 104 performs placement and routing based on the data including data on internal test circuit 103 and outputs placement and routing result data including placement and routing result data on test circuit 105.
As a technique for performing the circuit design using the procedure as described above, insertion of the test circuit in a stage of logic synthesis before the placement and routing and performing the placement and routing is described in Patent Document 1, for example. Patent Document 2 describes reconfiguration of a netlist of the test circuit so that efficient routing processing can be performed while considering placement positional relationships among cells after the cells have been placed. In this case, the routing processing for the test circuit is performed at the same time as that for the customer circuit.
[Patent Document 1] JP Patent Kokai Publication No. JP-P-2001-84280A
[Patent Document 2] JP Patent Kokai Publication No. JP-A-10-144796